Defect States Determining Dynamic Trapping-Detrapping in β -Ga 2 O 3 Field-Effect Transistors

β -Ga 2 O 3 is an intriguing material as a channel layer for the next generation high power transistors. To assess the device level effects of the traps in β -Ga 2 O 3 , the dynamic dispersion characteristics of a back-gated nanobelt β -Ga 2 O 3 ﬁeld-effect transistor prepared by mechanical exfoliation from a bulk β -Ga 2 O 3 single crystal was investigated by the dependence of threshold voltage hysteresis on transistor transfer characteristics on the gate voltage ramp, pulsed current-voltage characteristics, and current deep level transient spectroscopy measurements. Current lag in the off-state was related to the presence of electron traps at E c -0.75 eV, which are also present in bulk crystals and ascribed to Fe impurities or native defects. In the on-state, drain current lag was caused by surface traps with levels at E c -(0.95–1.1) eV. Optimized passivation layers for β -Ga 2 O 3 are required to prevent the current collapse because the device performances are affected by the environmental molecules adsorbed on the surface. Our work can pave a way to mitigating nonequilibrium on the traps for a long time, of the threshold voltage and drain current. Our results indicate that back-gated β -Ga 2 O 3 /SiO 2 /p ++ -Si nanobelt MOSFETs show attractive DC performance, with high satu- ration current, high transconductance, low subthreshold current, 9 but also exhibit drain current lag during channel modulation, hystere- sis in transfer transistor characteristics, and threshold voltage shifts nonequilibrium trapping. These are to the of deep electron and hole traps in the β -Ga 2 O 3 nanobelts β to the of the electron traps,

The high-voltage field-effect transistors (FETs) with an exfoliated β-Ga 2 O 3 nano-layer reported to date exhibit high on/off ratios and low subthreshold slopes. They can also be integrated with other low-dimensional materials, taking advantage of quasi-2D structures. Kim et al. 9 demonstrated combining β-Ga 2 O 3 nanobelts with h-BN, to fabricate a metal-insulator-semiconductor field effect transistor. Zhou et al. 21,23 fabricated nanobelt devices with various thicknesses to investigate the threshold voltage (V T ) shift tendency depending on the thickness of the β-Ga 2 O 3 nano-layer and found V T shifted from negative to positive direction as the thickness was gradually reduced. In this paper, we report on threshold voltage shifts and current collapse due to trapping effects by using the buffer-layer-free β-Ga 2 O 3 channel layer.

Experimental
Back-gated β-Ga 2 O 3 MOSFETs were prepared as shown schematically in Figure 1. Briefly, β-Ga 2 O 3 nano-layers with (100) orientation were separated from bulk undoped β-Ga 2 O 3 single crystals as shown in Fig. 1a, which were grown by the edge-defined film-fed method with (−201) orientation (Tamura Corp., Japan). The electron concentration in these crystals was 3.4 × 10 17 cm −3 , the dimension of the exfoliated flake was ∼63 μm in length∼ 40 μm in length, 3∼5 μm in width, and 200∼500 nm in thickness. These mechanically exfoliated nanobelts were dry-transferred on top of SiO 2 (300 nm)/p ++ −Si  Micro-Raman spectroscopy was performed under a back-scattering geometry using the 532-nm line of a diode-pumped solid-state laser (Omicron). The atomic structure and crystal orientations were characterized by transmission electron microscopy (TEM, G2 F30ST, Tecnai) after the specimen was prepared using focused ion beam (FIB) technique (Quanta2003D, FEI).
The fabricated device was wire-bonded for electrical measurements over the temperature range 77−400 K using a CF 4 gas-flow cryostat (Oxford Instruments, UK) or 300−500 K using a home-built hot stage. The electrical characterizations of the fabricated FETs involved static and pulsed drain current (I d ) versus drain voltage (V d ) characteristics at different gate voltages (V g ), I d -V g measurements at fixed V d , and gate current I g versus gate voltage (V g ) measurements for different temperatures, performed using B2902A (Keysight Technologies, USA) current/voltage source/meter. In pulsed I-V, 32 the measurements were performed with typical pulse length of 1 ms and period of 300 ms, with preset quiescent pulsed G-S (QV g ) and/or D-S (QV d ) voltages (i.e. before pulsed I d -V d measurement at the given V d , the gate and/or drain voltage was pulsed to QV g and/or QV d ). Defective traps in the FET structure were characterized by current deep level transient spectroscopy (CDLTS) with fixed drain voltage and pulsed gate voltage. 32 At each temperature, the current relaxation curve was captured and stored with pre-chosen time step and total monitored time length. The step in temperature between the current transient measurements was typically 0.1 K, the shortest time step available was 50 μs. These measurements allowed us to determine the characteristic relaxation times and current relaxation amplitudes during off-state and on-state conditions at different temperatures. 33 We also measured the spectra of drain current with optical excitation from a set of high-power (optical power 250 mW) light emitting diodes with wavelengths from 365 nm to 940 nm. 34,35 Results and Discussion Figure 2 shows the microscope image (Fig. 2a) of the fabricated FET along with Raman spectrum (Fig. 2b) of the exfoliated β-Ga 2 O 3 nano-layer deposited on SiO 2 /Si substrate. The phonon peak position of the exfoliated β-Ga 2 O 3 nano-layer is consistent with the β-Ga 2 O 3 crystal, showing the absence of strain-induced peak shifts. In addition, TEM image indicates that the crystal properties including the angle and the distance among the lattice atoms are well maintained after the mechanical exfoliation and the subsequent device fabrication processes as shown in Fig. 2c. The β-Ga 2 O 3 nano-layer transferred onto SiO 2 /Si substrate has (100)-face. Although monoclinic β-Ga 2 O 3 has two cleavage planes along (100) and (001), most flakes were separated along (100). Interestingly, the β-Ga 2 O 3 flake is in good contact with the underlying SiO 2 , causing no strain in the β-Ga 2 O 3 channel layer based on the Raman spectra (Fig. 2b) and the cross-sectional TEM image (Fig. 2c). Figure 3a shows the room temperature I d -V g characteristics measured for V g sweeping from −40 V to 0 V (red curves) and from 0 V to −40 V (blue curves). Zhou et al. reported the dependence of the thickness of β-Ga 2 O 3 flake on the FET performances, where a thicker flake resulted in a lower threshold voltage with a higher current density. 21 These were done with V g step of 0.1 V with waiting for 5 sec between the steps (slow ramp, solid curves) or 1sec (fast ramp, dashed curves). For the sweep from 0 to −40 V, the drain current is considerably higher for slow ramp rates, which is the result of contribution from electrons emitted from deep traps: at 0 V the traps are filled, at reverse bias they must be emptied, but the emission is slow so that the traps contribute to measured current at slow ramp, but not at fast ramp rates. For the opposite ramp direction (from −40 V to 0 V) and slow ramp rate, the current is systematically higher than for the 0 V to −40 V sweep, which indicates current transport without capture. However, the current for fast ramp rates in this case is again much lower than for slow ramp rates and considerably lower than the current measured with fast rates with the opposite V g sweep direction from 0 V to −40 V. This indicates the presence of centers with different properties, in which trapping of electrons involves overcoming an energy barrier. Such centers including surface or interface acceptors may cause upwards band bending at the surface of the n-type β-Ga 2 O 3 . The negative charge on the interface acceptors can shift the threshold voltage to positive direction and decrease the drain currents at the given gate voltage. The charge captured by the surface acceptors is supplied by electrons in the nanobelt. To be captured by the surface traps, these electrons have to overcome a barrier related to  surface band bending. This process is slow, resulting in lower drain currents for fast sweep rate. As the gate voltage becomes more positive, the surface barrier height decreases, making the process faster. Therefore, all the types of I d -V g curves converge at low gate voltage. As temperature is reduced, both the electron emission from deep bulk traps and the electron trapping by the surface acceptors become slower with less hysteresis, as illustrated in Fig. 3b (the positive shift of the threshold voltage as the temperature decreases is mainly due to the decrease of the electron concentration with decreasing temperature in the β-Ga 2 O 3 nanobelt. 36 Pulsed I d -V d characteristics show the effects of trapping. Figure 3c shows pulsed I d -V d characteristics at 25 • C with the base gate voltage V g = 0 V and different amplitudes of pulsed gate QV g and drain voltages QV d which precede pulsed I d -V d measurements at each V d . 34,35 The drain current is reduced when a high reverse gate voltage pulse QV g is applied before each measurement. The amount of drain current collapse induced by the reverse gate voltage pulsing should be close to the difference between the slow ramp and the fast ramp I d -V d branches, corresponding to the Vg sweep from −40 V to 0 V, i.e. to the channel opening after reverse gate voltage application. For room temperature and higher, drain voltage pulsing to high voltage has no effect on pulsed I d -V d characteristics, as expected. However, at low temperatures, V d pulsing separately or in conjunction with V g pulsing, does lead to additional decrease of the pulsed drain current (Fig. 3d).
To study the spectra of deep traps involved in drain current lag in the on-or off-states is to perform CDLTS measurements with channel closed or semi-closed and pulsed to on-state, or from on-state and pulsed to off-or semi-off state. 34,35 When the Ga 2 O 3 channel is kept at reverse gate bias, the parts of the deep electron traps in it are depleted of electrons. Removing the reverse gate voltage during the forward V g pulse fills the traps with electrons, which have to be emitted after the end of the pulse, producing an increase of the drain currents with time after the pulse. By monitoring the drain current relaxation curves at different temperatures and plotting the difference of drain current at time windows t 1 and t 2 , I d = I d (t 1 )-I d (t 2 ) (t 2 >>t 1 ), versus temperature, peaks corresponding to traps present in the material are obtained. The peak appears when the trap emission time rate e n becomes equal to 1/t 1 . 36 For exponential decay, the relaxation time τ corresponding to the peak is t 1 , while the peak amplitude is proportional to the trap concentration N t /t 1 . 36 By plotting the Arrhenius plot of ln(1/(τT 2 )) versus 1000/T, trap ionization level E a and the electron capture cross section σ n (here t for the peak temperature T is τ = t 1 ) are extracted. 36 Figure 4a shows CDLTS I d versus T spectra for the fabricated back-gated β-Ga 2 O 3 MOSFETs, measured with 1-sec-long V g = 0 V pulse applied to the semi-off state at V d = 5 V and steady-state gate voltage of −10 V, i.e. during the channel closing after the V g = 0V opening gate pulse. I d in the Fig. 4 are normalized to the steady-state drain current measured at each temperature. Since the drain current at (a) CDLTS spectra taken at V d = 5 V, V g pulse from −10 V to 0 V (1-sec-long) with time windows 2.4 sec/12 sec (solid curve, blue is the spectrum taken from 80 K to 400 K, dashed curve red is the high temperature spectrum measured on hot stage); (b) CDLTS spectrum taken with V d = 5 V, V g pulsed from 0V to −10 V for 1 s, time windows 100 ms/ 500 ms (c) Arrhenius plots for the E1, E2, E3, E4, and ST traps observed in CDLTS (d). Drain current spectra under illumination; the dark current is subtracted and the signal divided by dark current, measurements at V d = 5 V and V g = 0 V. −10 V is only slightly lower than the drain current for the fully open transistor, the peak magnitudes in such coordinates approximately correspond to the respective trap concentration N t normalized to t 1 , the donor doping N d , and (1-V g /V th ), i.e. N t /[t 1 N d (1-V g /V th )]. 36 Four peaks due to four electron traps E1, E2, E3, E4 were observed. The E a values with respect to the conduction band edge and electron capture cross sections σ n were E a = 0.6 eV, σ n = 6.6 × 10 −14 cm 2 (E1), ((0.71-0.75) eV, (1.1-17) × 10 −16 cm 2 ) (E2), 0.95 eV, 1.9 × 10 −14 cm 2 (E3), 1.25 eV, 5.8 × 10 −13 cm 2 (E4). These are the well-known E1, E2, E3, E4 electron traps detected in bulk n-Ga 2 O 3 37,38 and in n-Ga 2 O 3 epitaxial films grown by hydride vapor phase epitaxy (HVPE) 37−40 or molecular beam epitaxy (MBE). 41 For E1, E3, E4 traps, it is known that they are due to native defects or their complexes, 39,40 with E4 defects proposed to be related to oxygen vacancies. 39,42 There exist two types of defects with levels in the vicinity of the E2 trap, one due to Fe 37,39 and the other (E2 * 39 ) due to native defects. 39,40,42 The E2 trap is dominant in the fabricated β-Ga 2 O 3 MOSFETs and its concentration estimated from the magnitude of the CDLTS E2 peak normalized to the steady-state drain current and from the electron concentration in our material (3.4 × 10 17 cm −3 ) is on the order of 6.8 × 10 16 cm −3 .
The CDLTS spectrum for the on-state at V g = 0 V, V d = 5 V with pulsing for 1sec to V g = −10 V is shown in Fig. 4b (signal is again normalized to the steady-state drain current). One peak near 330 K with activation energy 0.95-1.1 eV (σ n = 10 −13 -10 −12 cm 2 ) is present. This activation energy likely corresponds to electrons being emitted from the surface acceptor traps (ST) responsible for the difference in the fast and slow ramp I d -V g curves taken for the V g sweep from −40 V to 0 V in Fig. 3a and for the drain current collapse in Fig. 3c. The observed activation energy characterizes the position of the filled surface states and is close to the Schottky barrier height in bulk and HVPE-grown films of n-Ga 2 O 3 . 37,39 This energy level is also not very different from another dominant bulk electron trap E3, which suggests that a certain amount of defect pinning occurs at the surface near defects also observed in the bulk of the films or crystals. For high temperatures the signal in Fig. 4b is hole-trap-like although the physical origin responsible is not clear. The density of the ST states is comparable to the E2 trap. Figure 4c shows the Arrhenius signatures of the detected traps (the observed spread is due to measurements with different time window sets and different samples).
Traps in the lower half of the Ga 2 O 3 bandgap are not expected to be recharged by electrical pulsing, but could adversely affect the electrical characteristics of the fabricated FETs after illumination. In Fig. 4d we show the drain current under illumination with high-power LEDs with photon energies from 1.3 eV to 3.4 eV, with the device biasing conditions of V g = 0 V and V d = 5 V. The dark current was subtracted and the signal was normalized to the dark current. Three prominent photocurrent features with optical thresholds near 1.35 eV, 2 eV, and 3.1 eV are present. These optical thresholds are similar to those reported for bulk β-Ga 2 O 3 crystals in deep levels optical spectroscopy (DLOS) and photocapacitance spectroscopy 38,41 and in proton irradiated HVPE films. 40 In the n-type materials, these transitions correspond to electron excitation to the conduction band, where the concentrations of the traps is ∼10 15 cm −3 . The midgap traps with optical threshold near 2 eV have a high barrier for capture of electrons. 38,41,42 If electrons are removed from these deep centers by illumination, the nonequilibrium charge created on the traps will persist for a long time, giving rise to drift of the threshold voltage and drain current.
Our results indicate that back-gated β-Ga 2 O 3 /SiO 2 /p ++ -Si nanobelt MOSFETs show attractive DC performance, with high saturation current, high transconductance, low subthreshold current, 9 but also exhibit drain current lag during channel modulation, hysteresis in transfer transistor characteristics, and threshold voltage shifts caused by nonequilibrium trapping. These phenomena are related to the presence of deep electron and hole traps in the β-Ga 2 O 3 nanobelts prepared from bulk β-Ga 2 O 3 single crystals and to the presence of surface or interface states. Among the electron traps, the most detrimental are the E2 electron traps near E c -0.8 eV present in concentrations of mid-10 16 cm −3 , which give rise to drain current transients during the channel pinch-off after temporary open. Hole traps with optical ionization threshold near 2 eV and concentration ∼10 15 cm −3 could cause drift issues after illumination with visible light. The defects are inherent in bulk Ga 2 O 3 crystals grown by different methods, 37,38 with E2 concentrations in such crystals in the high 10 16 cm −3 range, while the concentration of deep midgap hole traps is in the high 10 15 cm −3 range. 38,41 The E2 traps have been shown to be related to Fe, but there also are traps with levels near to E2 that are native point defects since they are also introduced by proton or alpha irradiation 39,40,42 (the E2 * traps 39 ). β-Ga 2 O 3 is not a van der Waals material, which implies that its surface contains a large number of the dangling bonds which are slow-states positioned at the deep level. Optimized passivation layers for mitigation of surface traps that affect the pulsed I d -V d and transfer I d -V g characteristics are also desirable.

Conclusions
Back-gated nanobelt β-Ga 2 O 3 /SiO 2 /p ++ -Si MOSFETs demonstrate promising DC performance, but exhibit dynamic dispersion behavior in pulsed I d -V d characteristics and trap spectra measurements, where an exfoliated β-Ga 2 O 3 inherit the characteristics of the single-crystal β-Ga 2 O 3 from which they were separated. Impacts of traps on the dynamic operation of the device were quantitatively investigated. Drain current lag is caused by electron trapping by E2 (E c -0.75 eV) centers originating in the bulk β-Ga 2 O 3 crystals used to fabricate the nanobelts, while drain current collapse in pulsed I d -V d characteristics, ramp rate dependence in I d -V g characteristics, and delay in transistor opening are the result of surface acceptors near E c -1 eV. Reduced the density of deep electron and hole traps will improve the dynamic behavior of the β-Ga 2 O 3 electronic devices.