Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

A review is given about the impact of the metal gate (MG) in a High- κ /Metal Gate (HKMG) stack on the quality and defectivity of the dielectric, assessed by low-frequency (LF) noise spectroscopy. In a ﬁrst part, processing aspects are discussed, like, the thickness of the MG and the implementation of a gate-last approach. In the latter case, it is shown that both the cleaning (or dummy gate removal), the growth of the interfacial SiO 2 layer (chemical versus thermal) and a post-HfO 2 -deposition heat or SF 6 plasma treatment need to be optimized for reducing the gate oxide trap density. In a second part, different MGs are compared from a viewpoint of noise magnitude. It is generally found that alternatives to the standard TiN gate yield better static and noise performance. Results will be presented both for scaled planar and FinFET technologies; the latter fabricated on either bulk or Silicon-on-Insulator (SOI) substrates. Also results on Gate-All-Around NanoWire FETs (GAA NWFETs) fabricated on SOI will be included.

It is well-established that the gate oxide quality and reliability strongly depend on the type of high-κ and interfacial oxide layer, the deposition method and the implementation of possible post-deposition annealing or passivation treatments. Low-frequency (LF) noise is a parameter which is very sensitive to the presence of traps and charges in the gate dielectric. [1][2][3][4][5][6] For large-area Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), the 1/f γ or flicker noise (γ∼1) typically found can be either due to carrier trapping in oxide traps (so-called n origin) 7,8 or caused by mobility (μ) fluctuations (socalled μ model). 9 For small-area transistors, the current fluctuations may become dominated by a single trap, resulting in so-called Random Telegraph Noise (RTN). 1,10 Both RTN and 1/f noise are commonly used to characterize traps in the gate dielectric, revealing their energy level, capture cross section and position with respect to the interface with the channel. 1,6,10 Assuming direct elastic tunneling of carriers, one can derive from a 1/f γ -spectrum an oxide trap density profile as a function of the depth, whereby an exponent γ = 1 indicates a uniform profile, while γ<1 or γ>1 corresponds with a trap density increasing or decreasing toward the interface. 6,[11][12][13][14] As a result, the low-frequency noise magnitude or Power Spectral Density (PSD) may be largely affected by the gate dielectric processing details, whereby it has been shown that the noise PSD usually increases when switching from SiO 2 or SiON to high-κ layers. [15][16][17][18][19] What is less studied is the impact of the gate material itself on the gate stack quality. The combination of a polycrystalline (poly) silicon gate with a high-κ dielectric leads to undesirable phenomena like Fermi level pinning and associated high threshold voltage (V T ) and poly depletion effects, which increase the Equivalent Oxide Thickness (EOT). In addition, the charges in the poly gate cause remote coulomb scattering of inversion layer carriers, which also results in a higher 1/f noise. [20][21][22][23][24] Replacing a poly gate by a metal gate (MG), therefore, generally results in a lowering of the 1/f noise PSD. Often, TiN-based MGs are being implemented. Early results indicate that the thickness of the TiN layer, defined by the number of Atomic Layer Deposition (ALD) cycles, has an impact on the noise PSD. 25 A reduction of the noise PSD was reported for a higher number of ALD cycles, i.e., a thicker TiN layer.
The present work reviews the low-frequency noise of High-κ/Metal Gate (HKMG) MOS transistors with emphasis on the role of the specific gate metal. Devices with different architectures (planar, Fin-FET and NanoWire (NW) FETs) will be addressed in addition to the gate first versus gate last (or replacement metal gate -RMG) integration. [26][27][28] Processing Impact In this part, the impact of the process implementation of a metal gate is investigated. First, the effect of the processing of a W plug or fill metal on the LF noise performance of planar 22 nm pMOSFETs is reported. A second example studies the impact of the thickness of the TiN layer on the noise performance of Silicon-on-Insulator (SOI) Multiple Gate FETs (MuGFETs). Finally, different processing aspects with respect to the implementation of an RMG will be addressed from a viewpoint of the noise performance, both for planar and FinFET transistors.
W plug processing.-The impact of the W plug processing on the LF noise of planar 22 nm CMOS compatible pMOSFETs is illustrated in Fig. 1. The gate dielectrics consist of a 0.8 nm SiO 2 interfacial layer and 2 nm HfO 2 deposited by Atomic Layer Deposition (ALD). The MG sandwich consists of 2 nm ALD TiN, 3 nm Ti deposited by Physical Vapor Deposition (PVD), 5 nm TiN fabricated by Metal Organic Chemical Vapor Deposition (MOCVD) and 75 nm ALD W, whereby two different processes have been studied, namely, using B 2 H 6 + W or SiH 4 + W precursors. The current noise PSD (S I ) has been measured in linear operation (V DS = −0.05 V), stepping the gate voltage V GS from weak to strong inversion (more negative values). The input-referred voltage noise PSD has been derived from the measured S I , through S Vg = S I /g m 2 , with g m the measured transconductance in each bias point.
As can be seen in Fig. 1, S I at a frequency f = 10 Hz versus the absolute drain current I D is higher for the B 2 H 6 precursor case, compared with the W deposition using SiH 4 as precursor. The higher input-referred voltage noise PSD is not caused by a difference in V T as the S Vg at flatband has been determined at V GS = V T , but is interpreted in terms of a higher oxide trap density, which is evidenced by the hump at about 100 μA drain current (I D ), which is thought associated with a gate oxide trap, causing a Random Telegraph Signal (RTS). The oxide trap density N ot is calculated from the 1/f noise PSD using: 7 with q the elementary charge; k B Boltzmann's constant and T the absolute temperature. Further, W and L are the device width and length, respectively, C EOT the capacitance density (F/cm 2 ) corresponding with the Equivalent Oxide Thickness (EOT) and α t the hole tunneling parameter in the gate oxide. It has been shown that the increase in S Vg at higher gate voltages can be interpreted in terms of the correlated mobility fluctuations model, 29 whereby the gate voltage dependence can be described by with S Vgfb the input-referred voltage noise PSD at flatband voltage (V FB ), α sc the coulomb scattering coefficient and μ eff the effective low-field mobility. The + or -sign depends on the nature of the oxide traps (donor or acceptor type). An example of such analysis is given in Fig. 2 for f = 10 Hz for both SiH 4 and B 2 H 6 precursors. It can be noticed that the B 2 H 6 W pMOSFET has a higher S Vg 1/2 , and in strong inversion, the S Vg 1/2 curve has a similar trend as the SiH 4 W device. The resulting S Vgfb and α sc for the SiH 4 and B 2 H 6 splits are summarized in Fig. 3. 29 As can be seen from the figure, the average S Vgfb is about one decade higher for the B 2 H 6 pMOSFETs, on the one hand due to the presence of more pronounced Generation-Recombination (GR) humps at f = 10 Hz, as found in Fig. 1. In addition, also the background 1/f noise PSD is higher, indicating a higher trap density in the oxide. These could possibly be related to the in-diffusion of B in the gate dielectric, which would introduce an acceptor state near the conduction band of the high-κ dielectric.
Another trend to be derived from Fig. 3 is the 4 times higher average α sc for the B 2 H 6 devices. This indicates that the charged oxide traps in the latter case are significantly more efficient coulomb scattering centers, possibly because they are on the average closer to the Si/SiO 2 interface. A higher α sc is usually found when the inversion layer charge is closer to the border traps in the oxide. This may support again B in-diffusion as a possible cause of the increased oxide trap density.
Information about the location of the generation-recombination deep traps can be obtained by studying the gate voltage dependence of the corner frequency, as shown in Fig. 4 for W plugs fabricated with the two different precursors. It can be noticed that for SiH 4 devices there is a strong gate voltage dependence of the Lorentzian peak maximum, indicating that the traps are located in in the gate oxide layer. On the other hand, the gate voltage independence of the corner frequency, corresponding with the peak maximum is characteristic for deep traps located in the depletion layer.
Impact of the TiN thickness on SOI FinFETs.-As mentioned before, the thickness of the TiN gate plays a crucial role in defining the threshold voltage and the LF noise of planar devices. 25 This has also been investigated for SOI n-and p-channel Multiple Gate FETs (MuGFETs), fabricated on a 65 nm film, a 150 nm Buried Oxide (BOX) thickness and with fin widths down to 25 nm. 30,31 The gate stack consists of a 1 nm SiO 2 IL and 2.3 nm MOCVD HfSiO. TiN capped with 100 nm polysilicon was used as gate electrode. The TiN thickness has been varied between 2 nm (64 ALD cycles), 5 nm (160 ALD cycles) and 10 nm (320 ALD cycles). The LF noise was measured in linear operation (50 mV).
The outcome of this study is summarized in Fig. 5a, 30 showing that the oxide trap density derived from S Vgfb increases with TiN thickness, contrary to the previous case. 25 At the same time, the low-field mobility μ 0 of the n-channel transistors is improved for smaller TiN thickness, indicating a correlation between the two parameters. This is again associated with a higher coulomb scattering factor, as more clearly shown in Fig. 5b, 30 which plots the inverse low-field mobility versus the coulomb scattering term qα sc N ot . The higher product α sc N ot corresponds with a lower μ 0 . The possible origin of the higher N ot with thicker TiN layer could be related with the higher oxygen scavenging ability, which leaves behind electrically active, "noisy" oxygen vacancy centers in the gate dielectric. 30 The possible influence of the EOT has been considered in order to calculate both the mobility from the Y-function method and the N ot . The impact of the TiN thickness on the analog parameters of MuGFETs has also been studied, indicating that a thinner TiN metal gate yields an enhanced voltage gain which can be attributed to the increased Early voltage. 31 Impact of RMG processing.-Implementation of a HKMG has become standard for state-of-the-art FinFET technologies. 32 Moreover, so-called high-κ-last or RMG integration schemes offer a wider process window for the deposition of metal-oxide cap layers to tune the effective work function and, hence, the threshold voltage. 33,34 This implies that a dummy amorphous or polysilicon gate and gate oxide need to be removed first, before fabricating the final HKMG stack. In order to enable the deposition of a good quality gate dielectric, effective pre-cleaning of the silicon surface is of vital importance. 32,33 Different types of pre-cleaning can be considered, 35 including standard diluted HF cleaning, a remote plasma (RP) cleaning in NF 3 /NH 3 called siconi 36 or a combination of the two. This was followed by an in situ O 3 oxidation to form an interfacial SiO 2 layer (IL-SiO 2 ). 35 Subsequent deposition of HfO 2 resulted in planar pMOSFETs with  an EOT of about 1 nm. A standard TiN gate with W fill metal was implemented. 35 A LF noise evaluation of the different oxide-removal steps revealed that the RP clean yields a significantly lower inputreferred voltage noise PSD, compared with the standard diluted HF clean, 35,37 indicating a better quality gate stack.
A second approach to improve the gate stack quality is by forming a good quality interfacial SiO 2 layer. Comparing a chemical oxide IL with in situ steam generated (ISSG) oxidation prior to HfO 2 growth has revealed a two times higher 1/f noise PSD for planar n-and p-channel MOSFETs, fabricated with an EOT of about 1 nm. 27 The gate dielectric consisted of a thin (<1 nm) SiO 2 IL (ISSG or ozone treatment) and between 2 and 2.5 nm HfO 2 . On the other hand, there was little impact of the HfO 2 thickness, varying between 2.0 and 2.5 nm nor the fill metal (W versus Al) on the average gate oxide trap density. 27 A final way to improve the quality of a RMG is by performing a post-deposition treatment. In Ref. 28, a post-deposition annealing (PDA) in N 2 at 500 • C for 1 min was compared with a post-HfO 2 -ALD SF 6 -plasma treatment for different times (3, 6 or 9 min), followed by the same PDA. This should introduce F in the gate stack, which is known to passivate oxide traps and reduce the 1/f noise PSD. [38][39][40][41][42][43][44][45][46] The investigated pMOSFETs had a 0.6 nm chemical (ozone) SiO 2 , formed after standard diluted HF clean, 36 ALD cycles of HfO 2 (∼1.8 nm thickness) and TiN gate followed by a fill metal. 28 As illustrated in Fig. 6, showing for the different process options the experimental data and median value, optimal noise performance was found for a 3 to 6 min SF 6 treatment, resulting in a clear reduction of the average noise PSD and the device-to-device variation.
Overall, combining a siconi removal of the dummy gate oxide, an ISSG SiO 2 IL and an SF 6 post-HfO 2 -ALD treatment of 3 to 6 minutes, followed by a 500 • C PDA should result in the lowest 1/f noise PSD for planar pMOSFETs, using a TiN metal gate. Finally, similar improvements in the LF noise PSD have been achieved for RMG p-type FinFETs after an SF 6 plasma treatment. 26,47

Different Metal Gate Materials
So far, the focus was on the integration aspect of a MG in the process flow, with TiN as the standard metal. However, it has been seen before that for example the thickness of the TiN layer can impact on the gate oxide quality, as probed by the LF noise PSD. The question arises what happens if TiN is replaced by another metal? Here, two examples will be given, showing that replacing TiN by an alternative material can drastically improve the LF noise and, hence, the oxide trap density.

TaN versus TiN in thick oxide IO pMOSFETs.-Input-Output
(IO) transistors for DRAM applications have traditionally been fabricated with a thick SiO 2 layer (∼5 nm) and a polysilicon gate. This yields a low 1/f noise PSD, corresponding with a low oxide trap density 48 and at the same time leads to a high Negative-Bias-Temperature Instability (NBTI) lifetime. However, these devices become more and more adopted to the processing of the peripheral logic devices, characterized by a HKMG stack. This implies that the polysilicon gate is being replaced by a MG (TiN) and that on top of the SiO 2 a HfO 2 layer is deposited. This is usually followed by a rather high DRAM thermal budget so that there is a good chance that the SiO 2 layer quality becomes degraded by the in-diffusion (or out-diffusion) of certain elements. As shown before, this indeed leads to a degradation of the LF noise PSD, an increase in the N ot and a degradation of the NBTI characteristics for IO pMOSFETs. 48 In order to improve the NBTI performance or even recover the original behavior for the poly/SiO 2 reference several process options have been considered, like, for example a post-deposition SF 6 plasma treatment 49 or replacing the TiN gate by TaN. 49,50 An example of the latter case is shown in Fig. 7, comparing the noise spectra of a 1 μm × 0.170 μm planar IO pMOSFET biased in linear operation (V DS = −0.05 V) at different gate biases and processed either with a standard HKMG stack (TiN/HfO 2 ) or with a TaN gate. As can be seen, the spectra are predominantly 1/f-noise like with some GR noise humps, occurring at different frequencies from device to device. As shown elsewhere, 50 the 1/f noise is dominated by number fluctuations, so that an oxide trap density (and profile) can be extracted from the noise spectra. It is also evident that in the case of Fig. 7, the TaN  gate pMOSFET has a significantly lower 1/f noise PSD compared with the TiN reference. This goes along with an improvement of the NBTI behavior. 49 However, another parameter which is relevant with respect to noise is its variation or spread across the wafer. Therefore, Fig. 8 gives the average input-referred voltage noise PSD at 10 Hz for a number of pMOSFETs arranged along the vertical diameter of both wafers. It can be observed that, while TaN-gate devices potentially have the lowest noise PSD, which is comparable to the poly/SiO 2 IO pMOSFETs, 50 the device-to-device spread is significantly larger, spanning more than a decade. It has been observed that this is related with the more frequent occurrence of excess GR noise at f = 10 Hz for the TaN devices. 50 Its origin is not clear for the moment but deserves future more detailed studies. For both TiN and TaN devices the f × S id spectra have been studied as shown in Fig. 9. Except for the higher noise level for TiN, a similar behavior is found for TiN and TaN, i.e., a similar frequency exponent of the spectra, implying in this case a more or less uniform oxide trap density in the frequency range studied. At the same time, the better NBTI behavior found for larger-area TaN pMOSFETs supports the idea that their gate stack quality is intrinsically better, i.e., corresponding with a smaller trap density. The physical origin of this observation is not clear but could point to a different oxygen scavenging by TaN compared with TiN.
In order to optimize the gate stack from a viewpoint of work function tuning and to improve the overall quality and reliability issues  much work has been performed on the use of capping layers and possibly the use of sandwich metal layers. The systematic study of the impact of capping layers such as Al 2 O 3 , LaO x and Mg, taking into account the location of the cap layer (above or below the gate dielectric) in relation to the dielectric layer and the thermal anneal budget, indicated that the noise PSD and its variability increase for capping layers underneath the gate dielectric and for higher anneal temperatures. 48,50 The impact of capping layers and metal gate structures is summarized in Fig. 10. Based on the median value for the different process options, it can be seen that 1) the TiN deposition technique (ALD vs PVD) has no real influence on the noise performance, 2) the impact of the Al 2 O 3 layer in combination with HKMG is limited, 3) the lowest noise level is obtained for TaN, and 5) the use of a sandwich structure TaN-TiN marginally influences the noise compared to the TaN case, while TaN-Al 2 O 3 -TiN seems to lead a small increase.

TiAl versus TiN in gate-all-around nanowire transistors.-Ul-
timately, the Gate-All-Around (GAA) nanowire (NW) architecture may take over at the end of the Roadmap due to the superior gate control over the short-channel effects. 51 Improved performance has been demonstrated for GAA NW n-and pMOSFETs fabricated on SOI substrates, compared with tri-gate FinFETs. 52 More interestingly, a pronounced impact of the metal gate has been noted as well. This is illustrated in Fig. 11 for the maximum transconductance g mmax of the n-channel GAA NW FETs. At the same time, it has been shown  that the 1/f noise PSD is significantly smaller as well (horizontal axis of Fig. 11), 53 confirming a general correlation between N ot and g m : a lower N ot goes hand in hand with a higher transconductance.
In order to understand better the origin of this strong impact of the metal gate, the noise spectra have been transformed into oxide trap density profiles versus trap depth with respect to the Si/SiO 2 interface. This is represented in Fig. 12, revealing an increase of N ot toward the metal gate for the TiN device, which is absent for the TiAl case. This suggests a possible oxygen scavenging effect of Ti on the gate stack, 54 creating an excess of "noisy" oxygen vacancy centers in the high-κ layer.

Summary
An overview has been given about the impact of the metal gate on the LF noise PSD of both planar FETs, triple-gate FinFETs and GAA NWFETs. In a first part, it has been demonstrated that the processing of a MG can have a significant effect on the overall gate stack quality. Both the metal gate fill processing, as well as the thickness of a TiN gate can modify the oxide trap density. Devices with B 2 H 6 + W processed gate metal were found to have a higher mean trap density and scattering coefficient than SiH 4 + W processed gate metal. For SiH 4 devices there is a strong gate voltage dependence of the Lorentzian peak maximum, indicating that the traps are located in the gate oxide layer. In the case of B 2 H 6 the traps are located in the silicon depletion layer.
Especially in the case of present-day RMG processing, one should carefully optimize the pre-cleaning (dummy gate removal) and the growth of the SiO 2 interfacial layer (IL). Post-high-κ treatments can also be implemented in order to improve the device performance and lower the 1/f noise PSD. An SF 6 plasma exposure followed by a PDA appears to be most successful in this.
Finally, the choice and most likely the deposition method of the metal gate can have a strong impact on the underlying gate stack. In the case of TiN, no significant difference has been observed between ALD and PVD deposition techniques. Replacing TiN by TaN results in a strong reduction of the average noise power spectral density. One of the key mechanisms is the oxygen scavenging potential of the metal in direct contact with the gate dielectric.

Acknowledgments
This work has been performed in the frame of imec's Core Partner Program on Logic Devices. The Institute of Microelectronics of the Chinese Academy of Sciences is thanked for supplying the planar pMOSFETs with different W plug processing. One of the Authors (L.H.) wants to acknowledge financial support by the China Scholar-