Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

As integrated circuits for high performance CMOS devices scale down to < = 10 nm dimension, further reductions in capacitance are vitally important for device performance. It is important to reduce capacitance in the FEOL and BEOL device structures while maintaining fabrication integration robustness. This paper presents an overview of material and process technology requirements for FEOL air spacer and BEOL air gap formation using a pinch off deposition approach. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume. The void dimension and volume in airgap/air spacer structures can be controlled with various dielectric deposition processes and materials to facilitate subsequent process fabrication steps, and ultimately to build a robust device with substantial capacitance reduction. © The Author(s) 2018. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0021811jss]

Continued integrated circuit scaling deeper into the nanoscale regime has provided improved performance through shrinking of the Front-End-of-Line (FEOL) device and the Back-End-of-Line (BEOL) interconnects. With scaling, resistance-capacitance (RC) delay is an increasing challenge, limiting overall product performance. Capacitance reduction is therefore vitally important for device performance in both the FEOL and BEOL device structure. Conventional capacitance reduction methods for FEOL and BEOL while maintaining yield and reliability have required significant material innovations. For example, the introduction of lower-k cap and bulk dielectrics with required mechanical, structural, electrical and other properties in device fabrication. To improve capacitance, other innovations in device structure and process integration such as Air Gap and Air Spacer are also needed. 1,2 For BEOL Airgap is one promising approach to reduce capacitance more significantly, as effective dielectric constants < 2.0 can be achieved. 3 Examples of alternate schemes with more modest C reductions have been reported 4,5 and have even reached manufacturing 6 in 14 nm node. FEOL Air spacers have long been recognized to provide the lowest effective dielectric constant Ceff. [7][8][9] The air spacer (FEOL) and air gap (BEOL) structures require novel process technology approaches such as pinch off deposition to optimize the capacitance reduction while maintaining yield and reliability. Pinch off deposition is a simple deposition of low to high conformality dielectric films over a spacing/gapped topological structure to form various void (Air Gap/Air Spacer) by closing off the top surfaces as typically showed in Figure 1. In first part of this paper, we report the fabrication of air spacer with FinFET technology at 10 nm node using pinch off deposition.
For BEOL, the metallization of integrated circuits for high performance CMOS devices involves the use of copper with low-k or ultra-low k dielectrics to reduce RC delay and cross talk in devices. Progressing from the 130 nm to the 14 nm CMOS device nodes, a conventional silicon nitride cap was replaced by new dielectric barrier low k materials such as SiCN, C-Rich SiCN and SiNO, [3][4][5][6][7][8] and Fluorine doped silicon oxide interlevel dielectric was replaced by low k and ultra-low k materials such as dense SiCOH and porous SiCOH. 12,[16][17][18] As devices scale down to < = 10 nm dimension, further reduction in capacitance for the Cu interconnect is and can be achieved by Air Gap 2 Fabrication in BEOL structures with enough mechanical strength, low leakage, good reliability and fabrication integration robustness.
In this paper, we also present an overview of material and process technology requirements for both FEOL air spacer 1 and BEOL air gap 2 formation using a pinch off deposition approach. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume as typically shown in Figure 1. For reference, the void dimension and volume in a typical air spacer/air gap structures can be controlled with various dielectric deposition processes and materials as in Figure 1: (a) Long and wide voids formation for optimal capacitance reduction. (b) Short and wide voids formation for improved process fabrication and integration. (c) Short and narrow voids formation for better sidewall protection and device reliability but with a smaller capacitance reduction. The overall void dimension and type of dielectric material are strongly related to the total device capacitance reduction and reliability. Significant capacitance reduction with good reliability has been achieved with the pinch off deposition process approach on current 10 nm device structures as shown in Figure 2b (FEOL Air spacer) and Figure 2b (BEOL Air Gap, 48 nm Pitch). The detail Air Gap and Air Spacer fabrication with specific structure and dimension, type of dielectrics, processes and device's performance will be discussed later in the paper.

Experiment-Film Deposition and Pinch off Process
The dielectrics of SiN, SiNO, SiCN, SiCOH, pSiCOH for pinch off deposition were deposited in a commercial high throughput production-worthy 13.6 MHz RF 300 mm Plasma Chemical Vapor Deposition process (PECVD) system at 350 C. The dielectrics were deposited using a combination of various silane (SiH4) or carbosilane or organosilicon precursors with other reactant gases such as Ammonia ((NH 3 ), Nitrogen (N 2 ), Oxygen (O 2 ), or Nitrous Oxide (N 2 O) as described in previous publications. [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] The advanced highly robust conformal SiN 6 was deposited by cyclic processing using Silane, Ammonia and Nitrogen. The SiCN dielectric was also deposited at 350 C using a combination of Trimethyl Silane (TMS) + Ammonia (NH 3 ) and (optionally) with Hydrogen for robust SiCN film. 15,19 For dense and porous SiCOH, liquid Octamethyl Orthosilicate (OMCTS) and Oxygen were used as precursors for the deposition at 350C 18 or 230-280C and UV cure 16 depending on the desired dielectric constant value and film's porosity. Overall, the plasma CVD temperature and the subsequent UV treatment for porous SiCOH are maintained about or below 400 C for both Air Gap and Air Spacer pinch off dielectric deposition to ensure no/minimal detrimental impact on the nano CMOS devices. The plasma deposition conditions  (rf power, pressure) and ratios of reactants were optimized to achieve good uniformity and optimal composition and bonding structure in the dielectric films. For barrier cap films such as SiN and SiNO, advanced cyclic multi-nanolayer deposition of the dielectric film was conducted with various surface treatments with Nitrogen and Nitrous Oxide plasma to achieve a high conformality as shown for SiN film in Figures 3 and 4. For highly conformal Cyclic multi nanolayer SiN or SiNO films, robust film sidewall protection can be achieved. 13,20 Figure 3 shows the details of the cyclic plasma deposition processes for conformal SiN and SiNO films. STEM pictures in Figure 4 show the typical cyclic multi nanolayer SiN or SiNO dielectric of highly conformal (>75%) sidewall protection over gate structure and then flowing with a second poorer/lower conformal low k dielectric to form the air spacer/airgap fabrication approach. In this cyclic process, the thin film (∼ 2 nm) deposition followed by plasma treatment provides excellent step coverage sidewall and then the poorer conformality deposition is for the pinch off deposition. For plasma deposited dielectric materials, the cyclic deposition and plasma treatment process improved the dielectric film's properties significantly. This first cyclic deposition/treatment step approach enables the change in the film's composition at nano dimension level and to enhance deposited film's sidewall conformality as indicated in our recent publications. 21,22 Table I summarizes various plasma deposited dielectric films and their properties. These dielectric films have been developed and used by our laboratories and have appeared in many of our publications 12-29 over the years. Since similar materials can be deposited under various conditions and have different properties, our reference publications [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] is to prefer to specific process chemistry and tooling that use for this pinch off deposition processes. These dielectrics are also commonly used by the semiconductor fabrication industry over the years in our review papers including various References 30,31. Historically, both Silicon Nitride and Silicon Oxide dielectric films have been widely used for electronic devices fabrication. In recent years, carbon and porosity have been incorporated to these dielectrics to reduce the dielectric constant and to create new classes of lower dielectric constant SiCN and SiCOH films that are now widely used for nano electronic device fabrication. 12,16,19,20 These dielectric films can also be used in the formation of air gap/air spacers for pinch off deposition. Table I shows several important dielectric properties, such as dielectric constant, conformality, porosity and carbon doping that have a strong impact on the pinch off deposition process. For the best optimal air gap/ air spacer formation, a two-step deposition process is normally used. In this study, conformality defines as the ratio of side wall/planar surface film's thickness over 1:1 aspect ratio structure as showed in Figure 4. In the first step, a thin robust conformal dielectric liner is deposited on the exposed top, sidewalls and bottom surface to  protect the reactive surface (metal liner, metal gate, silicide. . . etc.) elements. The first step dielectrics are normally conformal SiCN or SiN. In the second step, a non-conformal dielectric is deposited to pinch off the gaps to form air gaps/air spacer. The second step dielectrics are normally low k SiCN or SiCOH film. The type of dielectric associated thickness and film properties used in the pinch off deposition will have significant impact on the gap formation, and the resultant FEOL (air spacer) and BEOL (air gap) device capacitance reduction and reliability. With these two-steps deposition, there is always a consistent robust thin dielectric deposited to protect the top/sidewall/bottom surface of the air spacer/air gap, to prevent unwanted oxidation and to ensure reliability Scanning Electron Transmission Spectroscopy (STEM) and Electron Energy Loss Spectroscopy (EELS) techniques were used to examine the voids dimension by visual image and compositional detection. In next section, we will describe the fabrication, dimension and typical structures of both 10 nm Finfet Air Spacer 1 and 48 nm Pitch Air Gap in Cu-ULK 2 fabricated on many 300 mm wafers.
Two step Pinch off Deposition to form voids

Air Spacer and Air Gap Device Fabrication, Results and Discussion
For air spacer fabrication, a 10 nm FinFET CMOS platform 1 featuring contact gate pitch of 64nm, fin pitch of 42nm, replacement high-k/metal gate (RMG), and self-aligned contact (SAC) was used to develop an air spacer module that can be readily plugged into the standard CMOS flow. As depicted in Fig. 5a, the air spacer module is inserted in the FinFET flow after replacement high-k/metal gate (HK/MG) and source/drain trench silicide metallization (TS). Fig. 5b depicts the critical process steps for forming air spacers. The first step of air gap spacer formation is to remove a sacrificial gate caps and spacers after contact metallization. Reactive ion etching (RIE) process is used to remove the capping layer and spacer. It is required that not only gate metal but also contact metallization layer should not be eroded during the RIE process. The high aspect ratio structure (gate height/spacer thickness) in conjunction with high etch selectivity requirement for RIE pose a significant challenge for the removal of the layers. After forming the air gap, a two-step deposition process is used to form the air spacer. In the first step, a thin robust conformal dielectric liner is deposited on the exposed sidewalls of RMG and TS to protect the gate stack and TS metal. In the second step, a non-conformal dielectric is deposited to pinch off the gaps to form an air spacer. A planarization process is performed to remove dielectric above TS contact. The standard middle-of-line (MOL) process is resumed followed by back-end-of-line (BEOL) process to complete the transistor circuit fabrication. Figures 5c and 5d show a Scanning Transmission Micrograph of a fabricated 10 nm FinFET air spacer transistor and it associated graphical structures. It can be seen from Figure 5c that well shape-controlled air spacer structures can be fabricated with the steps in Figures 5a and 5b.
Since the air spacer dimensions are in nanometer scale, both STEM and EELS analysis techniques were used to detect, determine and measure the gaps such as between gate to source. Figure 6 shows both STEM image and EELS composition analysis of Air Gap X-section with 1nm conformal SiN and then 35 nm non-conformal pinch off deposition of SiCN dielectric. The STEM and EELS data confirm Air Spacer/Gap region dimensions. No or little Si/N/O signals as observed by STEM as voids.
The 10 nm Finfet device experimental data shown in Fig. 7 confirms the significant C gs (gate-to-source capacitance) reduction by  Comment on conformality: defines as the ratio of side wall/planar surface film's thickness over 1:1 aspect ratio structure as showed in Figure 4 SiO2 (Refs. 25   air spacers. The split was done by varying the RIE etching pulldown amount of low-k spacer and thus air spacer depth. Clearly more spacer pulldown results in more air spacer and thus more C gs reduction. The experimental data is in good agreement with TCAD simulation. The capacitance reduction is pronounced even when a very thin air layer is introduced in the spacer. Capacitance reduction of 50% can be achieved with 25% of air spacer. Capacitance reduction slows down with further increase in proportion of air portion. Therefore, a robust ultrathin dielectric like cyclic SiN or SiNO or SiCN liner to protect sidewall provides a good tradeoff between maximizing the benefit of air spacer while minimizing its reliability risk. TCAD simulation in Figure 8 confirms that our partial air spacer results in an equivalent k value of 3.2, significantly lower than any state-of-the-art low-k (k ∼5.0) spacer. Overall, partial air spacer (PAS) is a viable approach to introducing air spacer in FinFET, materializing the benefit of air spacer while minimizing its risks. In this approach, C gs can be reduced by 15-25% and C eff of Ring Oscillator by about 10-15%. 2 With the two-step pinch off deposition approach, no significant degradation is found in 10 nm Finfet air spacer transistor reliability.
For BEOL air gap formation, the baseline BEOL structure involves dual damascene Cu wiring in porous SiCOH ultralow-k (k = 2.4) dielectric 9 at minimum wiring pitch of 48 nm. The Cu wires have a Co/dielectric bilayer cap for EM lifetime enhancement, as was previously developed. 12,20 The BEOL airgap module utilizes relaxed lithography for airgap placement, while maintaining compatibility with the Co metal cap. The airgap integration module is depicted in   At these nm-scale dimensions, the Cu wire metal barrier and dielectric cap protection layers are highly critical for preventing any adverse interactions with the airgap processing. These layers are resistant to erosion, or chemical damage, and therefore protect the Cu wire itself. Any chemical attack must be avoided, as it can impact Cu wire resistance and reliability. The Co-Capping Cu process is followed by deposition of temporary hardmask and patterning stacks, and then lithographic patterning. Sequential dry and wet etch steps precisely etch back the interlayer dielectric in the desired locations. The hardmask stack is then completely removed, and an airgap robust protective dielectric barrier is deposited to seal the airgaps before the next low k (SiCOH 2.7 or pSiCOH 2.4 as in Table I) interlevel dielectric is deposited. For an optimal pinch off deposition process, either a single step robust SiCN dielectric deposition or a two-step conformal SiN/pinch off SiCN dielectric can be used to form the airgap. The single step pinched off deposition with robust dielectric is normally preferable due to the process simplicity and controlled cap thickness. Figure 10 show a typical structure of a 48 nm pitch Cu-ULK interconnect with SiCN dielectric pinch off deposition with a high and low plasma deposition pressures with the fabrication steps in Figure 9d. It can be seen from the Figure 10 images that the low pressure SiCN deposition process produced a better air gap with the pinch off below the Cu metal lines. This type of pinch off deposition with air gap below the Cu metal line is preferable for the subsequent fabrication steps. This is also enabling a larger process window for the air gap formation. Furthermore, this low-pressure SiCN film also provides additional advantage in k value reduction (∼5% k reduction) and subsequently will produce a slightly larger capacitance reduction in devices. Figure 11 shows STEM cross sections comparing wafers running the "ungapped" baseline process to those running the full airgap process with both blocked regions and airgapped regions. The gapped sections show typical 48 nm pitch airgap depths and profiles. Optimization of the airgap patterning process has resulted in minimal erosion of the Cu lines, to maintain reliability and resistance while demonstrating marked capacitance reduction. An additional advantage of our process, shown in this figure, is that the dielectric cap thickness is identical in both the blocked-out and airgap regions. This eliminates topography and vertical capacitance impacts of 2-barrier solutions used by others. It should be noted that we observed no issue in either placement of airgap adjacent to vias or the gapped vs ungapped space using this pinch off deposition in conjunction with the use of selective CVD Cobalt hard mask with optimal wet clean.
With the optimized airgap process with a single step pinch off deposition, a capacitance reduction of approximately 20% relative to the baseline process using ULK (k = 2.4) dielectric was achieved with no line resistance increase, as seen in Fig. 12. This data shows total capacitance (interlevel plus intralevel) for a multilevel comb-comb capacitor with airgaps applied to the entire array at one metal level. Typical capacitance reductions can be tuned to 15-25%, depending on the airgap depth. A capacitance reduction of ∼20% is achieved with no line resistance increase relative to the baseline ungapped process. Additionally, both TDDB and EM reliability are equivalent to ungapped controls. This is achieved 2 through careful control of the Cu protection, pinch off deposition and wet clean processes. This demonstrates the feasibility of extending airgap technology from the fat-wire levels into the thin/fine wire levels, even at advanced technology nodes using pinch off deposition as one of the processing steps.   In summary, as it has been shown in Figures 1a,1b,1c and 2a,2b, 6, 10, 11 that the pinch off deposition process with various dielectrics in Table I can be used to fabricated suitable voids of various shape and dimension. These two-step deposition process has been implemented into many 300 mm full functional test wafers with 10 nm FEOL Finfet air spacer and 48 nm pitch BEOL Cu-ULK device's structures. These optimized void fabrication technique with suitable process integration will generate a significant reduction in capacitance, boosting circuit performance while maintaining robust reliability with high device yield in many fully functional test wafers.

Conclusions
A pinch off deposition approach can be implemented to form voids suitable for capacitance reduction in nano device FEOL air spacer 1 and BEOL air gap 2 formation. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume. The void dimension and volume in airgap/air spacer structures can be controlled with various dielectric deposition processes and materials to facilitate subsequent process fabrication of robust devices with substantial capacitance reduction. Successful implementation of pinch off deposition in suitable process and integration approaches produces a significant capacitance reduction in both 10 nm FEOL Finfet air spacer and 48 nm pitch Cu-ULK BEOL structures. The capacitance reduction was obtained with improving device performance and without degradation in reliability.