Device Characteristics of AlGaN/GaN HEMTs with p-GaN Cap Layer

In this study, AlGaN/GaN high-electron-mobility transistors with a 5-nm p-GaN cap layer were investigated to compare their performance under various activation conditions. Speciﬁcally, p-GaN cap layers were activated using rapid thermal annealing at 700 ◦ C for 5, 10, and 15 min in an N 2 environment before device fabrication. The gate leakage current reduced considerably when the p-GaN cap layer activation time was longer. The measured on/off current ratio was improved to 9 × 10 7 for a Schottky-gate device with 15-min annealing time. The breakdown voltage was increased using the activated p-GaN cap layer. In pulsed I–V measurements, the device with the p-GaN cap layer with a 15-min activation time exhibited less current dispersion.

AlGaN/GaN high-electron-mobility transistors (HEMTs) have been shown to exhibit low on-resistance and high breakdown characteristics because of their high electron mobility and high breakdown field characteristics. AlGaN/GaN HEMTs on Si substrates are alternatives to Si transistors for power switching applications. However, a major problem for AlGaN/GaN HEMTs in power switching applications is current collapse, which is related to charge-trapping phenomena. Current collapse limits the output power and degrades the dynamic on-resistance (R ON ) of AlGaN/GaN HEMTs. 1 Major sources of current collapse have been identified in surface states and traps in epitaxial and buffer layers. Surface states near the gate edge can be charged while biasing into the off-state. When the device is switched on, the charged surface states cannot be immediately released, and partial two-dimensional electron gas (2DEG) in the channel is depleted, causing the device to exhibit high R ON . 2 Other studies have reported that the interface states at the insulator and semiconductor and that the traps at the epitaxial layers are problems that must be overcome. 3,4 A thin i-GaN cap layer is usually used to prevent oxidation and damage to the AlGaN barrier layer and maintain polarization for 2DEG purposes. However, device performance is still very sensitive to surface state filling during device processing. Careful deposition of a SiN passivation layer on top of AlGaN/GaN HEMTs has been studied and reported to improve current dispersion, breakdown, and output power. Derluyn et al. presented an in situ SiN method for passivating AlGaN/GaN devices in a metallorganic chemical vapor deposition (MOCVD) reactor before unloading the wafers. 5 AlN deposited as a passivation layer by using a plasma-enhanced atomic layer deposition system was shown to demonstrate excellent dynamic on-resistance. 6 Coffie et al. presented a novel p-capped GaN-AlGaN-GaN HEMT to reduce current dispersion before passivation. 7 Arulkumaran et al. studied an AlGaN/GaN modulation-doped field-effect transistor with different cap layers, namely i-GaN, n-GaN, p-GaN, and InGaN. 8 In those device structures, a doped AlGaN barrier layer was employed to form a 2DEG channel; this differs from the current AlGaN/GaN HEMT structure, which utilizes the polarization effect. Therefore, studying the effect of the cap layer on the performance of devices that utilize the polarization effect is critical. In the present study, AlGaN/GaN HEMTs with p-type GaN cap layers formed under different activation conditions were investigated to compare their effect on device performance. z E-mail: yhsin@ee.ncu.edu.tw  Figure 1 shows a schematic of the AlGaN/GaN HEMT structure under investigation. The epitaxial layers were grown on 4-in p-type Si substrates through MOCVD and were supplied by NTT-Advanced Technology Corporation. The epitaxial layers comprised a 300-nm GaN channel, a 1-nm AlN layer, a 20-nm Al 0.25 Ga 0.75 N layer, and a 5-nm GaN cap. The polarization-induced 2DEG density was formed at the AlN/GaN heterointerface. The 5-nm GaN cap layer was doped with Mg at a doping concentration of 1 × 10 19 cm −3 . According to X-ray rocking curve measurements, the full width at half-maximum (FWHM) values of the epitaxial wafer were 563 and 732 arcsec for the symmetric (002) and asymmetric (102) peaks of GaN, respectively. Hall measurements revealed the 2DEG mobility and density to be 1970 cm 2 /V-s and 1.004 × 10 13 cm −2 , respectively. The sheet resistance was estimated at 314.8 /sq before activation.

Device Structure and Experimental
Samples with the Mg-doped GaN cap layer were activated using rapid thermal annealing at 700 • C for 5, 10, and 15 min in an N 2 environment before device fabrication. Table I  values derived from X-ray diffraction measurements for samples with and without thermal activation. After activation, the FWHM values were found to be similar, indicating the same crystal quality. Table II summarizes the 2DEG mobility and density with and without thermal activation, as determined from the Hall measurements. The sheet resistances from the TLM measurement were respectively 310, 273, and 268 /sq for the samples with the 5, 10, and 15-min annealing times; these resistances were similar to those derived from Hall measurements. Lower sheet resistance was obtained after annealing, possibly because of thermal annealing at 700 • C. 9 After thermal activation, all samples were fabricated using the same layout and process flow. Dry etching with BCl 3 and Cl 2 mixed gas was performed to obtain a mesa isolation of 390 nm. The ohmic metal used was Ti/Al/Ti/Au, which was first evaporated using E-beam evaporation and annealed at 850 • C for 30 s to obtain low contact resistance. Prior to the deposition process, the wafers were dipped in diluted hydrochloric acid (HCl:H 2 O = 1:1) for 1 min to remove any oxide from the top of the wafer. The Schottky gate metal was obtained by evaporating a Ni/Ti/Al/Ti/Au stack through E-beam evaporation. No field-plate design was used in this process. All the devices under testing had a gate-source distance of 4 μm, a gate length of 2 μm, a total gate width of 2 × 50 μm, and a gate-drain distance (L GD ) of 8 μm. Devices with various L GD were fabricated simultaneously for a breakdown study. Finally, devices were passivated with a 200-nm SiN layer through inductively coupled plasma CVD at 200 • C.

Results and Discussion
DC I-V characteristics were measured using a Keysight B1505A semiconductor device parameter analyzer. Fig. 2 shows the output and transfer characteristics of the devices fabricated with a p-GaN cap layer activated under various conditions. The drain current (I D ) was found to have increased from 530 to 586 mA/mm at V GS = 1 V and V DS = 10 V after 15 min of activation at 700 • C, which corresponds to a −0.2-V shift in the threshold voltage. The increase in I D was because of the decreased sheet resistance. Fig. 3 shows the I D −V GS and I G −V GS characteristics in a semilog scale. The off-state current was dominated by the gate leakage current and found to decrease at longer annealing times. The gate leakage was effectively suppressed by the p-GaN cap layer after activation. The lowest I D was 6.5 × 10 −6 mA/mm; a Schottky-gate device exhibits an on/off current ratio of 9 × 10 7 .
The breakdown characteristics of the fabricated HEMTs with various L GD are shown in Fig. 4. The measured breakdown voltage was determined at I D = 1 mA/mm and V GS = −6 V with substrate floating. Because this study investigated the cap layer effect on device performance, substrate floating measurements were performed to alleviate the buffer/substrate effect on the breakdown voltage. For all of the fabricated devices, a linear increase in the breakdown voltage was observed as L GD was increased up to 10 μm. The devices fabricated under longer annealing times exhibited higher breakdown voltages. The inset in Fig. 4 shows the I D −V DS at off-state for devices with L GD of 20 μm. Lower off-state currents were observed in the devices fabricated under longer activation times, hence the higher breakdown voltages. The highest breakdown voltage was 1380 V, which was observed in the device with an L GD of 20 μm and activation time of 15 min. Because there was no field-plate design in the fabricated device, the highest electric-field was located near the drain-side gate edge. The 5-nm p-GaN cap layer was found to be crucial to reducing the leakage current and thus enhance the breakdown characteristics. Pulsed I-V measurements were performed using a Keysight B1525A high-voltage semiconductor pulse generator unit with a pulse width of 5 μs and a period of 1 ms. over, the pulsed I-V curves show a less pronounced self-heating effect compared with those in Fig. 2a. Higher current and lower R ON were obtained at room temperature. Because the highest electric field is located near the gate edge, surface states located near the gate edge can be charged while biasing into the off-state, causing current collapse. Fig. 5 shows that the devices with longer activation times exhibited less current dispersion, indicating that an effective suppression of electron injection into the trap states at the surface was achieved. Different quiescent bias points were also used to investigate the effect of off-state bias on transient I D . Transient I D was obtained at V DS = 10 V and V GS = 1 V from Fig. 5. Fig. 6 shows the normalized transient I D at various off-state drain biases. The transient I D decreased as the drain bias stress was increased from 10 to 40 V. However, improvement in the current drop was observed in the devices prepared under longer activation times.

Conclusions
AlGaN/GaN HEMTs with 5-nm p-GaN cap layers fabricated under various activation conditions were investigated. Three activation times were adopted for annealing at 700 • C (5, 10, and 15 min) in N 2 ambient, which was performed before device fabrication. DC I-V and pulsed I-V characteristics of all devices showed significant improvement in the device with a 15-min activation time. The device with the highest on/off current ratio of 9 × 10 7 showed a breakdown voltage of 1380 V. The electric field near the drain-side gate edge in AlGaN/GaN HEMTs is a critical factor related to the gate leakage current, off-state breakdown, and current collapse. In the present study, the p-GaN cap layer was found to be a viable alternative to i-GaN cap layers used in AlGaN/GaN HEMTs because it reduces the leakage current, improves the breakdown characteristics, and mitigates current collapse.