Mitigation of Arsenic Contamination on the Back Side of Si Wafer Using SiO 2 Protection Layer for III-V on Si Heterogeneous Epitaxy

In this paper, we have investigated a pathway to mitigate the arsenic (As) cross-contamination on a back side Si wafer during GaAs growth by metal-organic chemical vapor deposition (MOCVD). Without a proper protocol doing a III-V on Si heterogeneous epitaxy, we have observed high levels of the As concentration on the back side Si wafer, easily in excess of 1 × 10 20 atoms/cm 3 by secondary ion mass spectrometry (SIMS) analysis and 10 15 atoms/cm 2 by total reﬂection X-ray ﬂuorescence (TXRF) analysis, after GaAs growth on Si. This known level of contamination on wafers would disqualify them for fabrication in existing Si VLSI fabs. In order to mitigate the As cross-contamination, we have proposed a SiO 2 protection layer on the back side of the Si wafer. From both SIMS and TXRF analysis, the proposed scheme has dramatically lowered the back side as concentration to 1.5 × 10 16 atoms/cm 3 by SIMS and 1.0 × 10 10 atoms/cm 2 by TXRF.

III-V compound semiconductors have recently been explored as the most promising n-channel material for next-generation CMOS logic transistors. Especially, an indium-gallium-arsenide (InGaAs) material system has the spotlight due to its outstanding electron transport properties, relative maturity, and demonstrated reliability, compared with other candidates such as carbon nanotube transistors (CNTs) and semiconductor nanowires. [1][2][3][4][5] In fact, many research groups have paid attention to the InGaAs material system, and demonstrated excellent electrical characteristics of InGaAs metal-oxidesemiconductor field-effect transistors (MOSFETs). [1][2][3][4][5] Even with such notable improvements, what is critical at the end is to co-integrate those InGaAs materials with mainstream Si wafers and VLSI infrastructures in a heterogeneous integration fashion. Other approaches for integration of InGaAs materials, including wafer-bonding, are not as attractive economically. This strongly emphasizes that the InGaAs materials must be defined only in a certain area of the Si wafer for highperformance and low-power logic operations. Naturally, this calls for a selective epitaxy of the InGaAs material on the 300-mm Si wafer. In this regard, metal-organic chemical vapor deposition (MOCVD) is highly appropriate for the selective growth of the InGaAs onto the Si, as opposed to molecular-beam-epitaxy (MBE). 6,7 However, the use of MOCVD is not the complete solution for those Si wafers with selective growth of the InGaAs material to be successfully introduced in the existing 300-mm Si Fab. In addition, it is of critical importance to understand what kinds of new materials are present on both sides of the 300-mm Si wafers after the selective growth of the InGaAs layer is completed with MOCVD, to safely preserve the existing Si infra-structures.
Unfortunately, during the selective growth of the InGaAs material on the front-side of the 300-mm Si wafer, unwanted metallic cross-contaminations, such as As and Ga, occur on the back-side of the 300-mm Si wafer, which then seriously contaminates other infra-structures as the Si wafer are to be processed in many different toolsets. Among them, the As contamination is the most critical, since it is toxic, causes Environment-Safety-Health (ESH) issues and acts as an unwanted n-type dopants in Si. Also, such cross-contamination causes a detrimental impact on the performance and yield of the VLSI devices. For example, surface metallic impurities deteriorate the quality of the gate oxide, produce recombination-centers which increase junction leakage and degrade retention characteristics in DRAMs and z E-mail: dae-hyun.kim@ee.knu.ac.kr; hdlee@cnu.ac.kr increase dark currents in various image sensors. More seriously, the As atoms can easily penetrate into the Si wafer during the VLSI processing, causing a serious cross-contamination of the VLSI Si infrastructures. 8,9 Therefore, it is imperative to identify a pathway to mitigate the As cross-contamination after InGaAs growth by MOCVD before those InGaAs materials on Si wafers enter into the VLSI equipment, especially on the back-side of the Si wafer. In this paper, we first investigate the As contamination on the back side Si wafer during the selective growth of the InGaAs material, propose a protocol to effectively minimize the As contamination by a SiO 2 protection layer, and verify the usefulness of the proposed scheme using three different types of metrology.

Experimental
Two different types of 200-mm Si wafers with (001) orientation were prepared to evaluate the back side As cross-contamination after an 1.5 μm-thick GaAs layer was grown by MOCVD. One is without SiO 2 protection layer, and the other with 200 nm-thick SiO 2 protection layer deposited by plasma-enhanced chemical-vapor-deposition (PECVD) on the back side Si wafer. The MOCVD toolset used in this work is Aixtron-Crius which is capable of growing III-V materials on 300-mm Si wafers. Here, the reasons why we chose the GaAs are as follows: i) It has about 4% lattice mismatch to Si, which makes the selective growth of the GaAs on the Si wafer somewhat easier, and ii) It is very popular to grow GaAs layers by MOCVD for optoelectronic applications. Growth procedures for the GaAs layer are as follows: after dipping in 100:1 HF solution for 30 sec, a thermal cleaning of the Si surface was performed at 730 • C for 5 min in the H 2 ambient to remove native oxides in the MOCVD reactor. Subsequently, the substrate temperature decreased to 400 • C to uniformly initiate the nucleation of the GaAs seed layer, followed by high-temperature GaAs bulk-growth at 670 • C, 160 mbar. We have prepared four different samples to analyze the As contamination: Sample-A without oxide protection layer after GaAs growth, Sample-B without oxide protection layer after etching grown GaAs by wet chemical, Sample-C with oxide protection layer after GaAs growth, and Sample-D with oxide protection layer after etching the oxide protection layer by HF chemical solution. More details are provided in the next section.

Results and Discussion
In order to investigate the contaminations on the back side of two Si wafers, we have performed the transmission electron microscopy (TEM), secondary ion mass spectroscopy (SIMS) and total reflection X-ray fluorescence (TXRF) characterizations. Figure 1 shows crosssectional TEM images on the back side of both Si wafers after GaAs growth, without SiO 2 protection layer (Fig. 1a, sample-A) and with SiO 2 protection layer (Fig. 1c, sample-C). In each case, we dipped both wafers into a mixture of H 3 PO 4 /H 2 O 2 /DI (1/1/25) for 10 min after GaAs growth, aiming to intentionally etch the 1.5 μm-thick GaAs layers (Fig. 1b, sample-B). Finally, we dipped the sample-B wafer into an HF solution to etch the SiO 2 protection layer (Fig. 1d, sample-D). After GaAs growth on bare Si wafers by MOCVD, it can be seen that there were significant amounts of parasitic crystalline GaAs particle growths and formations on the back side Si wafer, as shown in Fig. 1a. However, those parasitic crystalline GaAs particles are too small to be inspected by SEM and optical microscope. Instead, we used the TEM analysis to visually identify those particles to begin with. As expected, the use of the amorphous SiO 2 protection layer on the back side of the Si wafer was effective in mitigating the parasitic growth of the GaAs layer since the adsorption of reactant species such as As and Ga would be reduced on the amorphous SiO 2 protection layer. This prohibits the nucleation of GaAs layer on the back side. Also, the use of the SiO 2 protection layer prevents pre-contaminated As particles from the susceptor of the MOCVD from diffusing into the Si wafer. At each stages, both SIMS and TXRF measurements were utilized to look into the distribution of the As atoms across the back side of the wafer. Figures 2a and 2b show the distribution profile of the As concentration on the back side of the Si wafers along the depth direction, by SIMS. Here, the primary raster size is 130 × 130 μm 2 and secondary analysis area has a diameter of 63 μm, respectively. For the wafer without SiO 2 protection layer, the As concentration is excessive on the back side, since the regions of the single-crystallized parasitic GaAs growth and cross-contaminations of the As from the susceptor occur, as discussed earlier. Interestingly, we find that there still exist significant amounts of the As atom distribution as high as 2 × 10 20 atoms/cm 3 on the back side surface of the Si wafer, even after we etch the wafer in a mixture of a H 3 PO 4 :H 2 O 2 :DI solution to remove the grown GaAs materials. This is because the As atoms have already been diffused into the Si wafer during GaAs growth at high temperature. As a result, there are a lot of As atoms inside the back side Si wafer with around 100 nm depth. However, when the SiO 2 protection layer is used on the back side prior to the GaAs growth, it leads to more than 10 3 times reduction in the As contamination on the back side of the Si wafer, as shown in Fig. 2b. After etching the SiO 2 protection layer by HF, it is also confirmed that the level of the back side As concentration measured by SIMS is less than 10 17 /cm 3 (Fig. 2b). Figure 3 shows the areal As concentration on the back side Si wafers by TXRF, using spot measurements with area of 500 × 500 μm 2 and scan duration of 500 sec. Compared to the average value of the Si wafers without SiO 2 protection layer (sample-A and -B), the As contamination of sample-B which has the H 3 PO 4 -based wet etching, yields a reduction from 1.97 × 10 14 atoms/cm 2 (sample-A) to 1.08 × 10 14 atoms/cm 2 (sample-B) which is similar to the  previous SIMS analysis (Fig. 2a). Nevertheless, the As concentration is still too high for these wafers to be introduced in the Si VLSI infrastructures. In contrast, when the SiO 2 protection layer is used on the back side Si wafer (sample-C), it is apparent that the back side As contamination significantly decreases to 1.53 × 10 13 atoms/cm 2 since the single-crystallized parasitic GaAs layer growth is effectively suppressed on the amorphous SiO 2 protection layer and there is a lot less diffusion of pre-contaminated As particles from the susceptor of the MOCVD. Furthermore, after etching the SiO 2 protection layer by HF-based solution, the amount of the As contamination decreases to 1 × 10 10 atoms/cm 2 (sample-D). Finally, Figure 4 displays the 2D wafer-mapping of the As concentration for all the back side Si wafers by using a rapid scan function in the TXRF measurement. This is a better way to diagnose metallic contamination across the wafer. Looking at As contamination for the same four different wafers, it can be seen that the overall As contamination is distributed very randomly across the wafer. In particular, the sample-D exhibits the lowest As contamination due to the mitigation of the parasitic growth of the GaAs layer by reducing the adsorption of reactant species such as As and Ga on the amorphous SiO 2 protection layer and its removal by HF solution. In order words, the As cross-contamination on the back side Si wafer is successfully controlled by the proposed protocol using the SiO 2 protection layer and its removal process. Nonetheless, it should be emphasized that we have routinely observed more As contamination at the edge of the wafer, calling for other schemes to effectively protect the edges of the wafer.

Conclusions
In this work, we have observed the significant As crosscontamination on the back side of the Si wafer after GaAs growth by MOCVD, in realizing the heterogeneous integration of InGaAs materials onto Si platform. In trying to eliminate this, we have successfully proposed the protocol using the SiO 2 protection layer on the back side and its removal process by HF solution. Having this protocol employed, the back side As concentration decreases to 1.0 × 10 10 atoms/cm 2 by TXRF. The results of this work show how to minimize contamination on the back side of Si wafers after III-V epitaxy, which will be an essential requirement for their introduction into VLSI infrastructures.