Low-Frequency Noise Assessment of the Oxide Trap Density in Thick-Oxide Input-Output Transistors for DRAM Applications

The impact of the implementation of a high-κ /metal-gate (HKMG) stack on the oxide integrity of input-output (I/O) pMOSFETs for DRAM periphery applications is investigated by means of low-frequency (LF) noise spectroscopy. It is shown that the predominant 1/f noise is governed by number ﬂuctuations, irrespective of the details of the gate stack. However, the trap density in the 5 nm SiO 2 gate oxide, derived from the noise power spectral density is signiﬁcantly increased by the application of the HKMG and/or Al 2 O 3 cap and the subsequent diffusion anneal at 900 ◦ C. © The Author(s) 2016. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http

Work function engineering by the introduction of cap layers in a high-κ gate stack 1,2 has been successfully implemented in logic and DRAM periphery MOSFETs.In the latter case, a so-called Diffusion and Gate Replacement (D&GR) integration scheme has recently been proposed. 3In this process flow, an Al 2 O 3 cap is inserted in the gate stack for tuning the threshold voltage V T of the p-channel transistors 2,4,5 and a Mg threshold-voltage shifter for n-channel devices.The metal atoms are then driven into the high-κ dielectric by a dedicated diffusion anneal step (which is typically carried out in the range of 600 • C to 900 • C 3 ) to form a dipole layer at the SiO 2 /HfO 2 interface, 1,2 which changes the effective work function and, hence, the V T .The doped dummy metal gates are subsequently removed and fresh TiN electrodes deposited.One concern with respect to the indiffusion of metal species into the high-κ gate stack is the preservation of the integrity and reliability of the oxide and its interface with the silicon substrate.
In addition to the thin Equivalent Oxide Thickness (EOT) peripheral transistors, input-output (I/O) devices with a thicker SiO 2 gate oxide need to be fabricated in a DRAM chip as well.These may also undergo the HfO 2 and Al 2 O 3 deposition and subsequent thermal budget in a HKMG process flow.The question addressed in this work is whether the thicker EOT devices suffer from the D&GR processing steps, from a viewpoint of gate oxide quality and reliability.To that aim, low-frequency (LF) noise is used as a tool to probe the border trap profile in the thick-oxide gate stack. 6,7It has been shown previously for thin-oxide DRAM periphery transistors that marked changes can be observed in the LF noise spectra of HKMG pMOSFETs with an Al 2 O 3 cap 8,9 or for nMOSFETs with a La or a Mg cap/shifter.Evidence will be given here for a strong increase of the oxide trap density in the 5 nm SiO 2 , derived from the 1/f-like noise spectra, when a high-κ and/or Al 2 O 3 cap layer is implemented.This could point to the in-diffusion of Al and/or Hf in the underlying SiO 2 layer, creating additional traps in the thermal gate oxide.At the same time, a degradation of the Negative Bias Temperature Instability (NBTI) has been noted, which correlates reasonably well with the average input-referred voltage 1/f noise power spectral density (PSD).

Experimental
P-channel transistors have been processed on 300 mm wafers following the conditions of Table I, with 5 nm SiO 2 + polysilicon gate as a reference.In the case of a high-κ/metal gate, about 2 nm HfO 2 and 5 nm TiN is deposited on top of the SiO 2 .The corresponding EOT and threshold voltage V T are represented in Table I.The Al 2 O 3 cap is deposited either below or on top of the HfO 2 and a diffusion anneal at 900 • C has been applied, like for the thin-oxide periphery transistors processed simultaneously.The last wafer split is the Diffusion and Gate Replacement (D&GR) CMOS scheme which has been recently successfully proposed. 3F noise measurements have been performed on W = 1 μm × L = 0.170 μm area devices in linear operation (drain-to-source voltage V DS = −0.05V) with the gate voltage V GS stepped from weak to strong inversion.About ten pMOSFETs per wafer have been measured in order to address the noise variability.The drain current noise PSD (S I ) and its normalized value (S I /I D 2 ) have been studied at a fixed frequency f = 10 Hz versus the drain current I D .The input-referred voltage noise PSD (S VG ) is derived from S I by dividing with g m 2 , with g m the measured transconductance.

Results
As shown in Fig. 1 for a reference Poly/SiO 2 pMOSFET, the noise spectra in linear operation and for different gate voltages V GS are typically 1/f-like, with occasionally excess Lorentzian noise components.Similar behavior is found for the other wafers.It is also clear, however, that the frequency exponent is close to 1 but varies slightly in the studied frequency range from 3 Hz to 100 kHz.At the same time, the normalized noise PSD at 10 Hz exhibits a variation of about one decade from device to device as shown in Fig. 2a.A larger spread may be observed for the other process splits (see below).At the same time, a hump is found in one of the curves of Fig. 2a, which can be associated with a Lorentzian Generation-Recombination (GR) noise component.Comparing S I /I D 2 with (g m /I D ) 2 in Fig. 2b, one observes that both characteristics are proportional with each other, indicating that the 1/f-like noise is due to number fluctuations. 10,11he trapping origin of the 1/f noise is confirmed for the HKMG wafer in Fig. 3, also showing higher values for the PSD and a larger spread compared with the reference Poly/SiO 2 devices of Fig. 2.This  implies that an oxide (or border) trap density (N bt ) can be calculated from the input-referred flatband voltage noise PSD (S VG ), using the formula: 10,11 In Eq. 1, q is the elementary charge, kT the thermal energy, C EOT the capacitance density corresponding with the EOT and α t the tunneling parameter, given by: 10,11 α t = 2 h 2qm ox it [2]   with h the reduced constant of Planck, m ox the tunneling effective mass in the gate stack and it the potential barrier for hole tunneling at the Si/SiO 2 interface.Typical values for α t are in the range of 10 8 cm −1 . 9The flatband voltage noise PSD can be derived from the more or less constant part of the S VG at 10 Hz in Fig. 4a (Poly/SiO 2 ) or Fig. 4b (HKMG) occurring around V T .At the same time, it is clear from the f × S I versus frequency plots in Fig. 5 that the frequency exponent is not constant but changes significantly with frequency.One can again clearly see that the magnitude is much higher for the HKMG pMOSFET and shows a much more pronounced 'profile', especially at low frequencies.Above 10 kHz, the values are more close to each other for both process splits.The increase with more negative V GS reflects the increase of the g m .As indicated, humps associated with GR noise (or Random Telegraph   Signals -RTS) can be present in the case of the HKMG transistor (Fig. 4b).

Discussion
The average input-referred voltage noise PSD at flatband for the different wafers is summarized in Figs 6a and 6b for a frequency of 10 Hz and 10 kHz.While the first data is representative of the trap density deep in the SiO 2 , at about 2 nm from the interface, the 10 kHz values are more representative for the near-interface SiO 2 layer.One can observe that the average value at 10 Hz is about one decade lower for the reference devices, compared with the HKMG counterparts, irrespective of the use of a cap layer.However, closer to the interface (10 kHz), the difference is less pronounced, although there is a tendency for a larger device-to-device spread in Fig. 6b compared with Fig. 6a.It is also clear from Fig. 6 that studying the average S VG at one frequency gives only a partial idea about the evolution of the trap density for the different process splits.In the case where a pronounced trap density profile is present, one should investigate the whole frequency range in more detail, as already discussed elsewhere. 12,13ssuming elastic tunneling, the frequency axis of a noise spectrum can be converted into a tunneling depth, using: 14,15 z = 1 α t ln 1 2πf τ 0 [3]   In Eq. 3, τ 0 is the Shockley-Read-Hall recombination lifetime at the Si/SiO 2 interface, usually on the order of 10 −10 s. 16 The oxide trap density profiles calculated from a spectrum at a gate voltage around V T for each wafer are represented in Fig. 7.The corresponding trap energy level approximately coincides with the valence band in silicon, since they have been obtained on p-channel transistors. 7t is evident that the HKMG pMOSFETs yield a trap density in the mid 10 17 cm −3 eV −1 range, significantly higher than for the reference SiO 2 device in Fig. 7.These trap densities are about one decade lower than typically found in high-κ materials, 8,9,12,13 so that the present gate stacks are somewhere intermediate pure SiO 2 and pure HfO 2 from a viewpoint of oxide trap density.The blue HKMG curve in Fig. 7 is suggestive for the in-diffusion of some species (Hf?) from the high-κ deposited on top of the SiO 2 , creating a decaying N bt profile toward the Si/SiO 2 interface.On the other hand, typical oxide defects responsible for 1/f noise are the oxygen vacancies, so that the increased N bt can also indicate a removal of oxygen from the thick SiO 2 layer by oxygen scavenging, for example. 17However, one should be cautious in over-interpreting Fig. 7: the spectra have not been corrected for the presence of GR noise humps, which could explain the increase of the HfO 2 curve in Fig. 7 and secondly, one has to consider also the device-to-device spread, reported in Fig. 6.This may result in a certain band of trap densities for each process split at each tunneling depth.However, the difference between the Poly/SiO 2 and the other splits is significant enough to be meaningful.Note, finally, the tendency for the trap density to reduce toward the Si/SiO 2 interface, which again points toward some in-diffusion process of the responsible traps.Whether this is related to an in-or an out-diffusing species cannot be decided based on the noise measurements alone and should be supported by some chemical analysis method.
It has, finally, been noted that the NBTI lifetime of the pMOS-FETs is significantly degraded by the presence of the HKMG and/or the Al 2 O 3 cap.This is represented on the horizontal axis of Fig. 8, showing the reduction in maximum overdrive voltage (V OV = V GS -V T ) for the different splits with respect to the Poly/SiO 2 reference.The lifetime criterion used is a V T shift of 50 mV.A higher reduction in V OVmax indicates a stronger degradation under NBTI.It is clear that the condition with Al 2 O 3 on top yields the smallest degradation (compared with the reference), while the D&GR splits corresponds with the strongest degradation.Interestingly, but not surprisingly, there appears to be a good correlation with the average 1/f noise PSD, as shown in Fig. 8: devices with the highest NBTI degradation also exhibit the highest average flatband S VG at 10 Hz for example.In other words, the 1/f noise PSD can be considered as an early indicator of the NBTI behavior of the pMOSFETs studied.In fact, it is by now well-established that there exists a strong correlation between 1/f noise and the NBTI relaxation transients, [18][19][20] since both are associated with pre-existing traps in the gate stack.The main difference is that NBTI probes a wider part (in depth and in energy) of the oxide trap density of states. 20,21

Conclusions
It has been shown that the deposition and subsequent diffusion anneal of a HKMG on top of the thick thermal oxide of I/O p-channel transistors for DRAM circuits degrades both the gate stack quality and reliability.This follows from the strong increase of the 1/f noise PSD with respect to the reference pMOSFETs with a Poly/SiO 2 gate stack.In parallel, the NBTI lifetime degrades significantly.Both phenomena can be interpreted by assuming a marked increase of the processinginduced oxide trap density in the SiO 2 .From the low-frequency noise measurements, an increase of N bt by about one decade on the average has been derived.

Figure 2 .Figure 3 .
Figure 2. (a) Normalized drain current noise PSD versus drain current at f = 10 Hz and in linear operation for a set of 1 μm × 0.170 μm pMOSFETs with standard Poly/SiO 2 gate stack.(b) Comparison of S I /I D 2 and (g m /I D ) 2 versus I D for one of the devices.

Figure 5 .
Figure 5. (a) f × S I versus frequency and in linear operation for a set of 1 μm × 0.170 μm pMOSFETs with Poly/SiO 2 or (b) HKMG/SiO 2 gate stack.

Figure 6 .
Figure 6.(a) Average flatband voltage noise power spectral density at 10 Hz and (b) 10 kHz for the different types of pMOSFETs studied.

Figure 7 .
Figure 7. Oxide trap density profile derived from the low-frequency noise spectra of one pMOSFET for each split at V GS ∼V T and V DS = −0.05V.

Figure 8 .
Figure 8.Average input-referred flatband voltage noise PSD at 10 Hz versus reduction of the maximum overdrive corresponding with a 50 mV NBTI shift in V T referred to the Poly/SiO 2 wafer (= origin).