III-V on Si Materials Surface Preparation and Process Control for Safety

This work studies the effect of wet chemical treatment of III-V based epitaxial layers. III-As high mobility channel materials are considered to be promising candidates and being evaluated for replacing Si NMOS channel in future CMOS devices to sustain further transistor and voltage scaling. Proper surface preparation, native oxide removal and post treatment surface stoichiometry are important when optimizing subsequent deposition of gate stack dielectrics. The results of liquid sampling of waste chemistries from experiments conducted in this work provide an insight into the solubility of InGaAs native oxides and resulting surface conditions. Additional information observed from the estimated etch rates and generation of arsine gas as a by-product of III-V materials interacting with the experimental chemistries allowed evaluating studied reactions for their manufacturability from the process control and safety points of view. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0301602jss] All rights reserved.

The potential of high mobility materials, in particular III-As-based compounds, is attractive for sustaining voltage scaling and providing an alternative to silicon-based CMOS technology in nodes beyond 14 nm. InGaAs channel materials provide a possible solution for integration into future nodes and are currently being considered as a viable material for future high mobility NMOS channels. 1 A wide range of direct-bandgap III-V materials are also attractive for integration with Si photonics due to superior optoelectronics performance, efficiency and ability to provide solutions for integrated laser and compact modulator. 2,3 Proper treatment of III-V materials surface prior to deposition of dielectrics or just removal of contaminants is considered one of the critical steps in new non-silicon technology. III-V materials tend to oxidize quickly when exposed to the atmosphere, forming both group III and group V native oxides on the surface. The first goal of a treatment is to efficiently remove these oxides while maintaining original crystalline film stoichiometry. The resultant post-treatment surface condition may affect both device performance and reliability. Treatment step is critically important for minimizing interface defect density as well as controlling contaminants such as the formation of mobile ions and limiting their possible diffusion into subsequently deposited dielectric layers.
In this paper we explore several wet chemical treatment chemistries for surface preparation of an In(0.53)GaAs layer on an InAlAs/GaAs buffer grown on a 300 mm silicon wafer. Investigated chemistries include DI water, concentrated and diluted HF, concentrated nitric acid, diluted HCl, diluted citric acid, diluted ammonia hydroxide and hydrogen peroxide. While XPS measurements is an accurate and sensitive method for detecting surface condition post wets treatment, we have chosen to analyze liquid samples obtained from the etch experiments for trace concentrations of As, In, Ga and Al. In this way we have eliminated the uncertainty created by re-oxidation after the treatment and obtained detailed data on the solubility of III-V elements in test chemistries. Observed concentrations were used to calculate and estimate etched layer thicknesses of In(0.53)GaAs layer and resulting surface stoichiometry in most cases as the result of native oxide removal with the assumption that a homogeneous oxide layer was present on the original epitaxial stack as it was exposed to normal atmosphere post epitaxial growth.
Experimental 300 mm wafer was used to deposit 10 nm undoped In(0.53)GaAs layer on the buffer layers grown by molecular beam epitaxy (MBE) * Electrochemical Society Active Member. z E-mail: alexey.vert@sematech.org on silicon substrate. The detailed description of all epitaxial layers including structure and thicknesses of the buffer layers is shown in Table I. This structure was chosen as one of the likely candidates for a realistic device prototype as it could be also grown on InP buffers with some layer modifications and includes larger bandgap channel back-barrier to enable channel charge confinement. Test wafer has been subsequently split into approximately one-by-one inch size samples and their dimensions were measured to calculate surface area of exposed III-V material. The experimental setup was designed to perform III-V on Si samples dip into test chemistries in an enclosed environment to capture all gases evolved from the reaction in order to analyze them for presence of arsine using Honeywell CM4 detector utilizing hydrides chemcassette and collect liquid samples of test chemistries. The details of the experimental setup are shown in Figure 1. Liquid samples were analyzed for concentrations of dissolved In, Ga, As and Al by ICP-MS technique which provides level of detection of less than 5 ppt by weight. The analysis was performed by Balazs NanoAnalysis analytical services with most abundant isotopes analyzed and reported for selected elements. The instrument used in this work was the ELAN DRC II, which utilized dynamic reaction cell technology to remove interferences and significantly suppress matrix effects. 4,5 Improved detection limits and reduced interferences were achieved by chemical resolution with typical detection limit and background equivalent concentrations reduced down to or below 1 ppt. In addition to internal yttrium standard calibration, external calibrations with traceable standards were also performed before and after each actual sample measured to ensure low detection error. Polyatomic interferences is a significant challenge when detecting trace metal concentrations, however ICP-MS technique has been already reported as a suitable method for determining dissolved In, Ga and As analytes and measuring their concentrations to study sub-nanometer etching of III-V substrates. 6 Each sample test sequence included opening the glove box and placing inside a clean beaker with the test chemistry as well as a beaker with DI water. III-V on Si sample was moved into the glove box as the last step and glove box was sealed. Samples were dipped into the test chemistries and then rinsed in the DI water, while arsine detector readings were continuously recorded with 10 second intervals. For most chemistries the air sampling intake was located in the vicinity of the test chemistry beaker to allow capturing reaction gases before they were getting diluted in the glove box air volume and ensuring highest possible sensitivity for detecting arsine. However, when experimenting with HF and HCl chemistries we found that chemcassette-based arsine detector was sensitive to their vapors and readings in the range of 0.5 to 15 ppb were observed when saturated vapors were present in the glove box air, especially when air sampling intake was placed immediately next to the beaker. In HF and HCl experiments arsine detection levels were limited, thus only large amounts were feasible to detect. This introduced a significant measurement noise floor for detecting small concentrations of arsine which was evolving as the result of the native oxide layer removal. The air intake flow rate was calibrated at 2 liters per minute and time dependent analysis of arsine detector readings allowed differentiating between false positive readings resulted from vapors interference and actual arsine readings by studying time constant of concentration decay during glove box air evacuation since the volume of the glove box was fixed. Table II summarizes results of the dip tests of III-V on Si samples into the test chemistries and analyzed concentrations of dissolved As, In, Ga and Al. All tests were performed at room temperature except one test conducted for concentrated HF acid at 60 degrees C for 1 minute dip time. Si material loss from the back side and re-deposition on the front side of the samples was neglected as we did not have evidence that evaluated chemistries were etching silicon material in conditions as tested.

Results and Discussion
Large amounts of arsine were detected when samples were subjected to concentrated HF acid at 60 C for 1 minute and concentrated HF acid at room temperature for 30 minutes. Arsine detector was saturated in these tests at 25 ppb due to the maximum concentration limit which could be measured by the hydrides chemcassette, and the actual released arsine concentration was assumed to be significantly higher in these tests. Large amounts of Al were found dissolved in the test chemistry likely due to the undercut through exposed edges of III-V on Si layers and it was concluded that Al-based III-V layers showed high etch rates in concentrated HF acid, which likely was the cause for the release of large amounts of arsine.
Special attention was paid in this work to investigating arsine release as it is being recognized as a critical safety issue and potential roadblock for scaling manufacturing of integrated with Si As-based high mobility channel materials on large size wafers. The release and evacuation of arsine in the glovebox-confined experiment was recorded for several hours when concentrated HF acid was used on the sample for 30 minutes. The detailed timing of arsine release showed some initial delay from the moment when the sample was dipped in the acid and can be explained by the time which was needed to significantly undercut through the edges of the sample and expose large areas of InAlAs layer to the test chemistry, after which the reaction continued at a very fast rate with immediate increase of arsine production, Figure 2. In general, edge effects were disregarded in this study in cases when amounts of produced arsine were non-detectable or chemical treatment time was low, however, when processes scaled to larger wafer size, it is expected that the condition of films at the edge of the wafer needs to be considered for each individual integrated step of the flow as normally done in CMOS fabrication. Given the size of the samples used to test treatment chemistries, the performed experiments potentially exaggerate effects, and at the same time do indicate problems expected to arise when concentrated HF acid is used on Al-based III-V epitaxial layers at prolonged times and elevated temperatures. Undercutting at the edge of the wafer and non-planar device structures through the layers which exhibit fast etch rates likely to result in foreign material and particle issues. Reviewing the delay in the time dependent arsine measurement from the tested sample does indicate that the directly exposed InGaAs layer at the front surface was the unlikely cause for forming arsine as it was not detected initially,  but as the undercut became significant, Al-based layer likely became the contributing source.
Arsine concentration was observed for several more hours after the sample was removed from the HF acid and rinsed in the DI water. It is likely that large amount of arsenic was left dissolved in the concentrated HF solution and produced outgassing of arsine that continued for prolonged amount of time. The recorded decay of glove box arsine concentration is shown in Figure 3 where the total amount of arsine gas generated from the tested III-V sample was estimated to exceed 60 microliters. It was also previously reported that Al-containing layers, and InAlAs in particular, show high etch rates in concentrated HF acid. 7,8 Nitric acid has shown high etch rate of tested III-V layers stack, where more than half of the III-V film thickness was consumed in 1 minute. There was no arsine detected as a by-product of this reaction.
Prior art and prior experimental results suggest that acids which were used in this work act as III-V oxide etchants and do show relatively low etch rates of the bulk III-V layers, except nitric acid. [7][8][9][10] Nitric acid also acts as a strong oxidizer and thus achieves high etch rates. We suggested a simplified scheme for describing the etching mechanism where two processes of oxidation and oxide etching need to be happening simultaneously in order to achieve etching of bulk III-V layers. Acids and DI water act as oxide etchants, while nitric acid, hydrogen peroxide and ammonia act as oxidizers. The schematic illustration of this scheme is shown in Figure 4. The native oxide of the top InGaAs layer is likely comprised of several oxide types for three elements In, Ga and As. The total composition can be quite complex and the exact chemical reactions describing interaction of these oxides with acids involves more than a few processes. In this work we accepted, previously found for HF and HCl acids, high etch rates for InGaAs oxides and relatively slow bulk InGaAs etch rate as the main assumption, suggesting that the etch process saturates after the native oxide is removed.
A more detailed analysis of the dissolved group-III and As species was done once we converted concentrations into the effective difference of remaining surface As, Ga and In relative to the ideal case stoichiometry corresponding to dissolved amounts. The results of these calculations are shown in Table III.
Changes in stoichiometry of resulting surface after the treatment are normally detected by X-ray photoelectron spectroscopy (XPS) measurements, 11 however in this work it was chosen to analyze liquid and calculate the resulting remaining surface stoichiometry ratio of In, Ga and As samples in order to evaluate and interpret posttreatment surface condition in experiments where no significant etch rate was detected. Liquid samples analysis is considered complimentary to previously reported XPS data and overall data interpretation was based on previously concluded ability of HF and HCl acids to efficiently remove native oxides. [9][10][11] One minute experiments showed that concentrated HF and diluted HCl may leave surface As-rich, while diluted ammonia hydroxide removes In at a slower rate than As and Ga. 30 minute experiment further confirmed observations for concentrated HF, diluted HCl and ammonia hydroxide. Diluted citric acid demonstrated more uniform InGaAs surface layer removal at both 1 minute and 30 minutes exposure. Hydrogen peroxide showed no etching, except small amounts of dissolved As detected, likely acting as an oxidizer of InGaAs layer. Isopropanol alcohol showed similar    Table IV. With this approach we assumed that the amount of material removed in DI water had thickness approximately corresponding to the thickness required for forming the layer of native oxide on InGaAs. Thickness of the native oxide was estimated from the high resolution transmission electron micrograph of the cross-section of the studied samples. Native oxide present on top of the InGaAs layer was found to be approximately 2 nm to 2.5 nm thick as shown in Figure 5. InGaAs layer atomic density for In, Ga and As is expected to reduce due to incorporation of oxygen when native oxide gets formed. The conclusions of the liquid sampling analysis may hint at a possibly different device performance if different wet treatment schemes are implemented due to different resulting post treatment InGaAs surface stoichiometry. It is likely that a single step treatment approach may not provide most optimal surface condition and a multi-step surface preparation will be required to achieve best results.

Summary
We found that tested acid based chemistries, except nitric acid and ammonia, demonstrated controlled removal of the top layer of the InGaAs layer corresponding roughly to the expected thickness of the native oxide based on the calculation derived from the approximation of the etched III-V layer mass. The assumption was made based on the prior data that the etch rates of the bulk of III-V layers stack are insignificant. However, etch rates of III-V layers in concentrated nitric acid and Al-based layers in concentrated HF were found to be high enough to require chemistry dilution for better etch process control.
Additionally, as most of the tested chemistries are available in standard 300 mm silicon fab tools likely to be used in manufacturing, important aspects of chemical safety and compatibility with III-V on Si materials processing has been addressed in the scope of detection of arsine as a by-product of chemical reactions. Chemistries have been evaluated for their safety, need for control and risk mitigation. Al-based III-V layers seemed to produce large amounts of arsine when concentrated HF acid was used. The use of HF chemistry will require monitoring of arsine gas release in the reaction chamber of the wet processing tool in order to ensure that any out-gassing is correctly addressed and operator is not exposed. The need for arsine monitoring, modifications of the processing chambers to sustain negative pressure all the times and required post-processing outgassing and toxic gas monitoring, which is wise to consider for all other wets processing as well, is not posing a manufacturing prohibiting problem, but does increment complexity and costs. With proper design, process and environmental controls authors believe that studied chemistries and materials can be used in high volume manufacturing on 300-mm wafer size substrates.